코아시아넥셀 Design & DV Engineer 모집

■ About CoAsiaNexell Design group

CoAsiaNexell provides comprehensive development services from spec consultation to chip design and software.
The CoAsiaNexell Design Group handles from spec consultation to the RTL hand-off stage of the chip design process. We collaborate on the back-end implementation to contribute to the GDS out and participate in the silicon bring-up process to achieve product success.

□ Design engineer
As a proactive worker, a CoAsiaNexell Design Engineer performs the following tasks.

○ Review and discuss specifications, then design/verify and make reports for an AMBA-based routable design that meets these specifications
○ Participate in backend implementation and the silicon bring-up process to identify, support, and provide guidance on issues.
○ Prepare documentation related to design deliverables for co-workers.
○ Read, summarize, and work on specifications, IPs, and guides written in English, and participate in meetings and communication in English
when necessary
○ Languages and Tools Used:
→ HDL languages such as Verilog and System Verilog, and design constraints like SDC and UPF.
→ EDA tools (e.g., Xcelium, VCS, Design Compiler, PrimeTime, SpyGlass, and other EDA tools).
→ scripting languages such as TCL, Perl, Ruby and Python. C language for Embedded SW.
→ Tools necessary for documentation such as LaTeX, MS Office, and other relevant tools.

Additionally, the following roles are expected for Senior Design Engineers and Intermediate Design Engineers:
※ Senior Design Engineer (10+ years)
A Senior Design Engineer demonstrates technical leadership and contributes to the success of the team and product by working with engineers in their department. They also foster strong relationships with department engineers to support their growth.

※ Intermediate Design Engineer (5+ years)
An Intermediate Design Engineer contributes to the success of the team and product by assisting junior engineers in their department, in addition to managing their own tasks.

CoAsiaNexell Design Engineers are generally divided into specific parts, each responsible for subsystems that include related IPs.
Preference is given to candidates with relevant experience in each part.

Senior Design Engineer for Highspeed IF. Part
→ PCIe, USB, MMC, QSPI
Intermediate Design Engineer for CPU Part
→ Cortex-A/M/R series and related IP like GIC/Coresight/SECJTAG/Power Management Unit
Intermediate Design Engineer for Highspeed IF. Part
→ PCIe, USB, MMC, QSPI
Intermediate Design Engineer for Video/Camera Part
→ RGB/MCU Parallel Interface, CPI, MIPI CSI & DSI and other display IPs like HDMI or DP
(Note) GPU/Codec IPs are in Multimedia Part.
Intermediate Design Engineer for System/Peri Part
→ PMU, Peripherical IP like SPI/I2C/UART, PMU, SCP
in-house tool like IOMUX/CMU/SYSREG/CFG_BUS generator or RTL Integrator
(Note)System/Peri Part engineer need to responsible for in-house tool also.

□ CoAsiaNexell DV Engineer
CoasiaNexell DV Group supports the chip design to find the bug through development. Also We contribute to success of product with designer to support Silicon bring-up.

● Qualifications include:
○ BSc in Electrical Engineering or Computer Engineering with 3+ years of experience in ASIC Design Verification or MS in Electrical Engineering or
Computer Engineering with 1+ years of experience in ASIC Design Verification
○ Deep knowledge about System Verilog, UVM and verification coverage matrix
○ Experienced in developing checker, scoreboard & writing assertions.
○ Prior experience and knowledge of ARM core, AMBA bus protocol, Serial peripherals (eg: USI), High Speed Peri (eg: PCIe, Ethernet), Memory
(eg:LPDDR/DDR4/4x/5, GDDR5/6), Video(eg: MIPI, Codec), Security
○ Familiarity with generating randomized vectors for analog and digital behavioral model verification.
○ Hands-on knowledge of standard industry EDA tools - Synopsys/Cadence.
○ Working knowledge of Assembly, C, and C++ languages and use in embedded systems
● Highly Desired Qualifications:
○ Strong written and verbal communication skills, with the specific ability to speak to various technical and management levels.
○ Proactive, collaborative and creative approach to innovation, technical development and consensus facilitation to influence optimal project
results.
○ Excellent time and task management, and interpersonal skills.
○ Communication skills in English with the other part like Design Group or VN site
● What will make you stand out:
○ Excellent knowledge of PCIE protocol - Gen3 and above is a plus
○ Very high speed SerDes IP verification experience is a nice to have
○ Knowledge of IEEE 802.3 Physical layer clauses like Cl.72, 93, 91 etc. is a plu

■ 복리후생 제도
- 자율 출퇴근제
- Refresh 휴가지원금
- 어학지원금
- 중, 석식비 및 교통비 제공
- 설, 명절, 기념일 선물
- 月 1회 Family day
- 직원 단체보험
- 그룹사 유명 콘도 할인 제공
- 사내 동호회
- 기타 포상(우수사원, 장기근속, 경조금 지원 등)